Semiconductor Electronics: NEET and JEE questions with solutions

Answer: (B) $2$ V

The reverse-biased Zener is in breakdown, since $5\ \text{V} > 3\ \text{V}$. An ideal Zener then holds a constant $3$ V across itself (between C and B).

The rest of the supply voltage appears across the resistor R, which lies between B and A:
$$|V_B - V_A| = 5 - 3 = 2\ \text{V}$$

Solution by Sreeraj P, M.Sc Physics

Answer: (C) $W_3 > W_2 > W_1$

c

Solution by Sreeraj P, M.Sc Physics

Answer: (D) NOR

The upper gate is a NOR gate: its output is $\overline{A + B}$.

The lower gate is a NAND gate: its output is $\overline{A \cdot B}$.

The final AND gate gives
$$Y = \overline{A + B}\cdot\overline{A \cdot B} = (\bar{A}\bar{B})(\bar{A} + \bar{B}) = \bar{A}\bar{B}$$
since $\bar{A}\bar{B}\bar{A} = \bar{A}\bar{B}$ and $\bar{A}\bar{B}\bar{B} = \bar{A}\bar{B}$.

$Y = \bar{A}\bar{B} = \overline{A + B}$, which is the NOR function.

Solution by Sreeraj P, M.Sc Physics

Answer: (B) $D_1$ is reverse biased, $D_2$ is forward biased

At $t = 15$ ms: $100\pi \times 0.015 = 1.5\pi$, and $\sin(1.5\pi) = -1$. The input is at its negative peak, i.e. in the negative half cycle.

In a centre-tap full wave rectifier, $D_1$ conducts during the positive half cycle and $D_2$ during the negative half cycle.

So at $t = 15$ ms, $D_1$ is reverse biased and $D_2$ is forward biased.

Solution by Sreeraj P, M.Sc Physics