Semiconductor Electronics question for JEE Main (JEE Main 2026 (2 Apr, Shift 2)), with solution

Answer: (D) NOR gate

A NAND gate with both inputs joined acts as a NOT gate.

First stage: the outputs are $\overline X$ and $\overline Y$.

Second stage (NAND): $\overline{\overline X\cdot\overline Y}=X+Y$ (OR, by De Morgan's theorem).

Third stage (NAND with inputs joined, i.e. NOT): output $=\overline{X+Y}$, which is a NOR gate.

Solution by Sreeraj P, M.Sc Physics